ISBN 9788126536948,Digital System Designs & Practices:Using Verilog Hdl & Fpgas

Digital System Designs & Practices:Using Verilog Hdl & Fpgas

Author:

Ming-Bo Lin

Publisher:

Wiley India

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ISBN 9788126536948
Publisher

Wiley India

Publication Year 2012
ISBN-13

ISBN 9788126536948

ISBN-10 8126536942
Binding

Paperback

Number of Pages 836 Pages
Language (English)
Subject

Computer Engineering

Table Of Contents
Chapter 1 Introduction.
1.1 Introduction.
1.2 Introduction To Verilog.
1.3 Module Modeling Styles.
1.4 Simulation.
Chapter 2 Structural Modeling.
2.1 Gate-Level Modeling.
2.2 Gate Delays.
2.3 Hazards.
2.4 Switch-Level Modeling.
Chapter 3 Dataflow Modeling.
3.1 Dataflow Modeling.
3.2 Operands.
3.3 Operators.
Chapter 4 Behavioral Modeling.
4.1 Procedural Constructs.
4.2 Procedural Assignments.
4.3 Timing Control.
4.4 Selection Statements.
4.5 Iterative (Loop) Statements.
Chapter 5 Tasks, Functions And Udps.
5.1 Tasks.
5.2 Functions.
5.3 System Tasks And Functions.
5.4 User-Defined Primitives.
Chapter 6 Hierarchical Structural Modeling.
6.1 Module.
6.2 Generate Statement.
6.3 Configurations.
Chapter 7 Advanced Modeling Techniques.
7.1 Sequential And Parallel Blocks.
7.2 Procedural Continuous Assignments.
7.3 Delay Models And Timing Checks.
7.4 Compiler Directives.
Chapter 8 Combinational Logic Modules.
8.1 Decoders.
8.2 Encoders.
8.3 Multiplexers.
8.4 Demultiplexers.
8.5 Magnitude Comparators.
8.6 A Case Study: Seven-Segment Led Display.
Chapter 9 Sequential Logic Modules.
9.1 Flip-Flops.
9.2 Memory Elements.
9.3 Shift Registers.
9.4 Counters.
9.5 Sequence Generators.
9.6 Timing Generators.
Chapter 10 Design Options Of Digital Systems.
10.1 Design Options Of Digital Systems.
10.2 Pld Modeling.
10.3 Cpld.
10.4 Fpga.
10.5 Practical Issues.
Chapter 11 System Design Methodology.
11.1 Finite-State Machine.
11.2 Rtl Design.
11.3 Rtl Implementation Options.
11.4 A Case Study: Liquid-Crystal Displays.
Chapter 12 Synthesis.
12.1 Design Flow Of Asics And Fpga-Based Systems.
12.2 Design Environment And Constraints.
12.3 Logic Synthesis.
12.4 Language Structure Synthesis.
12.5 Coding Guidelines.
Chapter 13 Verification.
13.1 Functional Verification.
13.2 Simulation.
13.3 Test Bench Design.
13.4 Dynamic Timing Analysis.
13.5 Static Timing Analysis.
13.6 Value Change Dump (Vcd) Files.
13.7 A Case Study: Fpga-Based Design And Verification Flow.
Chapter 14 Arithmetic Modules.
14.1 Addition And Subtraction.
14.2 Multiplication.
14.3 Division.
14.4 Arithmetic And Logic Unit.
14.5 Digital-Signal Processing Modules.
Chapter 15 Design Examples.
15.1 Bus.
15.2 Data Transfer.
15.3 General-Purpose Input And Output.
15.4 Timers.
15.5 Universal Asynchronous Receiver And Transmitter.
15.6 A Simple Cpu Design.
Chapter 16 Design For Testability.
16.1 Fault Models.
16.2 Test Vector Generation.
16.3 Testable Circuit Design.
16.4 System-Level Testing.
Appendix A Verilog Hdl Syntax.
A.1 Keywords.
A.2 Source Syntax.
A.3 Declarations.
A.4 Primitive Instances.
A.5 Module And Generated Instantiation.
A.6 Udp Declaration And Instantiation.
A.7 Behavioral Statements.
A.8 Specify Section.
A.9 Expressions.
A.10 General.
Index.
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