|Number of Pages||376 Pages|
|Dimensions (Cms)||21.5 x 14 x 1.5|
The purpose of VHDL Modeling for Digital Design Synthesis is to introduce VHSIC Hardware Description Language (VHDL) and its use for synthesis. VHDL is a hardware description language which provides a means of specifying a digital system over different levels of abstraction. It supports behaviour specification during the early stages of a design process and structural specification during the later implementation stages. VHDL was originally introduced as a hardware description language that permitted the simulation of digital designs. It is now increasingly used for design specifications that are given as the input to synthesis tools which translate the specifications into netlists from which the physical systems can be built. This book is designed for working professionals as well as for graduate or undergraduate students. Readers can use this book to get acquainted with VHDL and to learn how it can be used in modeling of digital designs.