| Publisher |
Springer Nature |
| Publication Year |
2014 |
| ISBN-13 |
9783319071381 |
| ISBN-10 |
9783319071381 |
| Binding |
Hardcover |
| Number of Pages |
590 Pages |
| Language |
(English) |
| Weight (grms) |
1020 |
This book is a comprehensive guide to assertion-based verification of hardware designs using System Verilog Assertions (SVA). It enables readers to minimize the cost of verification by using assertion-based techniques in simulation testing, coverage collection and formal analysis. The book provides detailed descriptions of all the language features of SVA, accompanied by step-by-step examples of how to employ them to construct powerful and reusable sets of properties. The book also shows how SVA fits into the broader System Verilog language, demonstrating the ways that assertions can interact with other System Verilog components. The reader new to hardware verification will benefit from general material describing the nature of design models and behaviors, how they are exercised, and the different roles that assertions play. This second edition covers the features introduced by the recent IEEE 1800-2012.
Eduard Cerny
Eduard Cerny received M.Eng. and Ph.D. degrees in electrical engineering from McGill University, Montreal, in 1970 and 1975, respectively. From 1978 until 2001 he was a professor in the Department Computer Science and Operations Research at the Universite de Montreal. He published and was a consultant in areas related to the specification, simulation, formal verification and test of microelectronics systems and in the development of CAD tools. He joined Synopsys, Inc., in 2001. Currently he is a Scientist in the Marlborough, MA, office as member of the Synopsys Verification Group. His responsibilities include design-for-verification methodology, in particular as related to assertions, with four patents in that area. He was co-chair and member of the IEEE P1800 System Verilog Assertions committee and a co-author of the books Verification Methodology Manual for System Verilog (Kluwer 2006) and The Power of System Verilog Assertions (Springer 2010).
Eduard Cerny
Springer Nature