Static Timing Analysis For VlSI Circuits

Static Timing Analysis For VlSI Circuits

Author :

R. Jayagowri

,

Pushpendra S. Yadav

Publisher:

Medtech Publishers

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Publisher

Medtech Publishers
Publication Year 2024
ISBN-13

9788196544560
ISBN-10 8196544561
Binding

Paperback
Edition 2nd
Number of Pages 226 Pages
Language (English)
Dimensions (Cms) 24X18X2
Weight (grms) 362

The book “STATIC TIMING ANALYSIS FOR VLSI CIRCUITS” is prepared in focus of explaining the Timing concepts of Integrated circuit design in simple language. It helps undergraduate and postgraduate degree students of electronics stream those who are interested to work in ASIC design. The book may also help the industry engineers, who can use it as STA quick reference. The fresh engineers of the industry, interested to work in IC timing analysis can use this as a startup guide. It can be used as a textbook for the Static Timing Analysis course, for undergraduate and postgraduate circuit branch student's community of all  universities and it can also be used as a good reference book for the course titled ASIC design. The book is written in such a manner to provide comfort to all kind of readers.


The features of the book are:


•    All required basic concepts are explained in the beginning and before starting of  Timing analysis.


•    The Synopsys Primetime® commands to write the constraints for timing analysis are explained with all its options.


•    For the ease of understanding of commands and concepts, the good examples and diagrams are provided.


•    Sample Timing reports are provided to make the reader to visualize and understand the different timing checks  can occur during the process of chip design using EDA tool.


•    The important feature of the book is that it provides the knowledge on major techniques to fix the timing violations with sample reports for before and after fixing violations.


At the end of every chapter it includes some solved problems, collection of questions. It may be very helpful for the students to crack their  interview on Static Timing Analysis.

R. Jayagowri

Ms. R. Jayagowri is an Associate Professor in the Department of Electronics and Communication Engineering, BMS College of Engineering, Bangalore, India. She pursued her Ph.D degree in the field of Low power VLSI Testing from Jawaharlal Nehru Technological University, Hyderabad and she received her M.E. degree in Applied Electronics from the College of Engineering Guindy, Anna University, Guindy, Chennai, India. Her interested research area is Low power VLSI Testing, Static Timing Analysis and VLSI Physical Design. She published her research papers in different reputed conferences and journals. She also received patents, all India level and state level awards for her projects. She is author of two VLSI books. She is a senior member IEEE, Life member of IETE and ISTE. She is an active contributing member of technical conferences.

Pushpendra S. Yadav

Mr. Pushpendra S. Yadav is working as an Associate Technical Director in Samsung Semiconductor, India. He has an impressive background more than 15 years in SoC, IPs & ASIC design with extensive experience in various aspects of VLSI design. His educational qualifications, including M.Tech degree in Microelectronics and Embedded Systems from JIIT, Noida (U.P. India) and B.E. degree in Electronics and Communication Engineering from MITS, Gwalior (M.P. India), provide a strong foundation for his career in semiconductor (VLSI) design. He has worked with companies like Qualcomm Semiconductor, Cypress Semiconductor, NXP (Formally known as Philips Semiconductor) Semiconductor & Intel Technology which demonstrates a diverse range of skills in various domain like Constraints Development, Static Timing Analysis, Power Analysis, Synthesis, RTL Design and Physical Design. He published multiple papers in many conferences. It's clear that he has a solid foundation in the field of semiconductor design.
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